Electronic systems are becoming a staple of modern life. These electronic systems may be very simple systems, such as individual logic gates that are used for simple control circuits, moderately complex systems, such as integrated logic circuits that are used for controllers and embedded processors, or much more complex systems utilized in powerful computing architectures.
Almost universally, the power requirements for these electronic systems have been increasing. This is especially true when referring to microprocessor based computing systems. Besides the display, the largest consumer of power in a computing system is the CPU microprocessor, and the higher the clock frequency of the microprocessor the greater that microprocessor's power consumption (all other aspects being equal). Prior techniques for reducing the power consumption of a microprocessor have reduced the speed of the system clock (or turned off the clock altogether) during periods of inactivity. These techniques, however, are costly because of the additional complicated circuitry needed for the storing and restoring of the state of the computer when the system clock is turned off.
Additionally, these techniques do not account for situations where an executing program must wait for an event, for example, while doing I/O polling or lock acquisition. In these cases, programs have traditionally executed a timing loop such as:
/*An example of a timing loop*/void delay(unsigned long loops) {  while (loops--)  ;}
In a timing loop such as this, the processor executing the program will execute a “nop” instruction during the timing loop, consuming power though in actuality the program is waiting for the completion of another task. For example, on a microprocessor which operates at a system clock speed of 10 GHz, waiting for an I/O instruction for 10 PCI bus cycles (33 MHz) while executing such a timing loop is equivalent to wasting 3,000 CPU clock cycles.
On a multi-threaded processor these problems become exacerbated. Timing loops not only waste processor power, they also consume unnecessary execution clock cycles which other threads could utilize. On a multi-threaded processor the actual time period of a timing loop may change depending on the activity of concurrently executing threads. This problem has traditionally been addressed by executing a timing loop utilizing a counter which changes in value. This counter is usually implemented using a special purpose register or memory mapped I/O. An example of such a timing loop is:
/* from linux-2.4.20/include/asm-ppc64/delay.h *//* define these here to prevent circular dependencies */#define ———HMT_low( )  asm volatile(“1,1,1”)#define ———HMT_medium( )  asm volatile(“or 2,2,2”)static inline unsigned long ——get_tb(void){  unsigned long rval;  asm volatile(“mftb %0“=r” (rval));  return rval;}static inline void -delay(unsigned long loops){  unsigned long start = ——get_tb( )  while ((——get_tb( ) -start) <loops)  ———HMT_low( ):}
This timing loop is specific to the PowerPC architecture, as it uses the “mftb” instruction to access the TBL time stamp counter. Consequently, this loop may allow a program to approximate specific waiting times. However, these time periods may only be based on the system clock utilized in conjunction with the microprocessor, and, because such a loop must use processor specific instructions (mftb) the code is not portable across processor architectures.
Another methodology for queiscing processors during idle periods is to provide a halt instruction for the microprocessor. An example of a conventional halt instruction for the PowerPC architecture is depicted in FIG. 1. Halt instruction 100 has opcode 110 value of nineteen in bits 0-5 and extended opcode 120 value, resident in bits 21-30, of five hundred and thirty.
Usually a halt instruction of this type stops instruction execution on a processor until a timer or I/O interrupt occurs, and are used by operating systems when there is no process to execute. These instructions are usually required to set up interrupts. Setting up these interrupts may be expensive (requiring many instructions). Additionally, these halt instructions may only be executed by system (privileged) software, and do not allow the instruction to specify the amount of time for which the processor is to stop instruction execution.
Thus, a need exists for a method and system for a user to instruct a microprocessor to cease execution of instructions which can specify the clock to utilize, the number of clock cycles to halt, and which does not impede the execution of other threads on a multi-threaded microprocessor.